The drive toward miniaturization presents many challenges for the IC packaging industry. These challenges are partly addressed through use of leadless lead-frame packages (LLPs), which reduce the footprint and height of IC packages by eliminating leads that protrude from the sides of a package, instead employing contacts that are electrically exposed yet lie flush with an outer surface of the package. An LLP is a surface mounted IC package that uses a metal, usually copper, lead-frame substrate to both support the IC die and provide electrical connectivity. As illustrated in FIG. 1A and the successively more detailed FIGS. 1B and 1C, in known LLPs, a copper lead-frame strip or panel 101 is patterned, usually by stamping or etching, to define two dimensional arrays 103 of device areas 105. Each device area 105 is configured to support a semiconductor die. In the illustrated embodiment, each device area 105 includes a die attach pad 107 and a plurality of contacts 109 disposed about their associated die attach pad 107. Very fine tie bars 111 are used to support die attach pads 107 and contacts 109 during manufacturing. Although the thickness of the metal sheets from which the LLP lead-frames are made may vary, a typical thickness may be on the order of 8 mils (0.008″) thick.
During assembly, IC dice are attached to respective die attach pads 107 and electrically connected to the contacts 109 using conventional wire bonding techniques. After wire bonding, a plastic encapsulant cap is molded over the top surface of each device area individually, or over each array 103. The capped dice are then cut from the array and tested using known sawing and testing techniques.
FIG. 2 illustrates a cross-section of a semiconductor die 200 after it is attached to the die attach pad 107 and bond wires 202 are bonded to the contacts 109. Commonly, an adhesive 204 such as a conductive silver-filled epoxy is deposited on the upper surface 206 of the die attach pad 107, and the die 200 is pressed onto the adhesive 204. In so doing, the die 200 is affixed to the die attach pad 107, but excess adhesive 204 may also be displaced. In some processes, the displaced portion of the adhesive 204 may be pushed completely off the die attach pad 107 where it flows down to the lower surface 208, thus creating exposed conductive areas 210 on the bottom of a packaged IC. While the amount of adhesive 204 shown, and the amount that has spilled down onto surface 208, is exaggerated for purposes of explanation, it is nevertheless a reality that the creation of conductive areas 210 is a risk. Such conductive areas risk electrical damage to the die 200, reducing process yields and creating potentially defective packages. Additionally, because the surface area of the upper surface 206 is relatively large, differences in the thermal expansion coefficients of the die 200, epoxy 204, and die attach pad 107 can result in a buildup of shear stresses along the upper surface 206. With continued thermal cycling this can sometimes result in delamination of the adhesive 204 from the die attach pad 107 and/or the die 200.
Although the prior art packaging techniques work well, there are continuing efforts to provide even further improved package designs.